互補式金氧半算術運算電路之分析及設計

Chaoyang University of Technology Institutional Repository > 資訊學院 > 資訊工程系 > 博碩士論文 > Item 310901800/25570

Please use this identifier to cite or link to this item: http://ir.lib.cyut.edu.tw:8080/handle/310901800/25570

Title:	互補式金氧半算術運算電路之分析及設計 Analysis and Design of CMOS Arithmetic Circuits
Authors:	林漢忠 Lin, Han-Chung
Contributors:	資訊工程系碩士班張原豪 Yuen-Haw Chang
Keywords:	比較器;乘法器;加法器;優先編碼器;矽智財;增量器/減量器 comparator;adder;multiplier;silicon intellectual property;priority encoder;incrementer/decrementer
Date:	2005-12-31
Issue Date:	2015-11-07 10:33:03 (UTC+8)
Abstract:	隨著半導體製程技術的快速發展，以及電子產品往系統單晶片(System on Chip, SoC)的趨勢發展，使得晶片設計的工作日益複雜。因此，透過設計及重複的使用矽智財(Silicon Intellectual Property, SIP)來完成晶片設計，將有效加速設計時程及節省成本。本論文的製程技術是使用台積電0.35μm CMOS 2P4M來完成電路模擬及晶片的實體佈局。論文中首先完成優先編碼器IP，基於優先編碼器IP完成了二個適用於高速度操作的互補式算術運算電路，分別是比較器及增量器 / 減量器。在加法器的電路設計上，主要是採用「多階層摺疊」及「對角線前傳」等兩種設計技巧。在乘法器的部分，設計一個具有自動補數偵測功能的串-並乘法器。經由Hspice的電路模擬及晶片的量測結果，顯示優先編碼器、加法器、乘法器、比較器及增量器 / 減量器，在性能的表現上均優於傳統式電路。 Due to the rapid development of semiconductor fabrication technique and the trends of System-on-chip-based (SoC-based) electronic products, the integrated circuit design becomes more and more complicated. Therefore, the reusable Silicon-intellectual-property (SIP) is desired, because it could shorten a great deal of design time and cost. This thesis is considered in Cadence environment for achieving pre- layout / post-layout simulation based on 0.35μm CMOS 2P4M process of TSMC. First, the priority encoder IP design is performed, then based on this encoder IP, both high-speed comparator and incrementer/decrementer are realized. Besides, the pre-layout / post-layout design of an adder is implemented by the use of multilevel folding and diagonal forwarding techniques. Finally, the serial-parallel multiplier with automatic complement detection is proposed. From the results of Hspice simulation and chip testing, the suggested priority encoder, adder, multiplier, comparator, and incrementer/ decrementer show the pretty better performance than that of traditional circuit scheme.
Appears in Collections:	[資訊工程系] 博碩士論文

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